The present invention relates to communication systems supporting synchronous voice services, more particularly to the use of continuous variable slope delta modulation/demodulation in such systems, and even more particularly to techniques for making continuous variable slope delta modulation-based systems more robust in the presence of interference.
In the last decades, progress in radio and Very Large Scale Integrated Circuit (VLSI) technology has fostered widespread use of radio communications in consumer applications. Portable devices, such as mobile radios, can now be produced having acceptable cost, size and power consumption.
Although wireless technology is today focused mainly on cellular communications, in which a user is connected to a fixed infrastructure via radio base stations and portable handsets, a new area of radio communications is emerging that provides short-range connectivity between nomadic devices like laptop computers, mobile phones, Personal Digital Assistants (PDAs) and digital notebooks. Further advances in technology will provide very inexpensive radio equipment, which can be easily integrated into many devices. This will reduce the number of cables currently use to interconnect devices. For instance, radio communication can eliminate or reduce the number of cables used to connect master devices with their respective peripherals. The aforementioned radio communications will require an unlicenced band with sufficient capacity to allow for high data rate transmissions. A suitable band is the Industrial, Scientific and Medical (ISM) band at 2.45 GHz, which is globally available. The ISM band provides 83.5 MHz of radio spectrum.
By definition, unlicensed bands allow all kinds of radio systems to operate in the same medium. This gives rise to mutual interference. To reduce interference and allow a fair access for every user, signal spreading is usually applied. Spreading provides immunity to other systems to other systems and jammers sharing the band. In fact, the Federal Communications Commission (FCC) in the United States currently requires radio equipment operating in the 2.45 GHz band to apply some form of signal spreading when the transmit power exceeds about 0 dBm. Spreading can either be at the symbol level by applying a direct-sequence (DS) spread spectrum technique, or at the channel level by applying a frequency hopping (FH) spread spectrum technique. The latter is attractive for the radio applications mentioned above because it more readily allows the use of cost-effective radios. A radio interface, called BLUETOOTH(trademark) wireless technology, has recently been introduced to provide pervasive connectivity, in particular, between portable units like mobile phones, laptop computers, PDAs, and other nomadic devices. The BLUETOOTH(trademark) system applies frequency hopping to enable the implementation of lowpower, low-cost radios having small physical dimensions (xe2x80x9ca small footprintxe2x80x9d). The system supports both data and voice services. The latter is optimized by applying fast frequency hopping with a nominal rate of 800 hops per second (hops/s) through the entire 2.45 GHz ISM band in combination with a robust voice coding. An introduction to the BLUETOOTH(trademark) system can be found in xe2x80x9cBLUETOOTHxe2x80x94The universal radio interface for as hoc, wireless connectivity,xe2x80x9d by J. C. Haartsen, Ericsson Review No. 3, 1998.
The default voice coding scheme in the BLUETOOTH(trademark) system is based on Continuous Variable Slope Delta (CVSD) modulation. CVSD modulation is a type of delta modulation. More generally, delta modulation is a waveform coding technique in which an analog signal is sampled and the difference between successive samples (delta step) is represented by a binary word (bit sequence) that is subsequently transferred to the recipient. The coded bits in the delta modulation do not represent an absolute signal level but rather a derivative. In fact, the bits typically only tell the recipient to go one step up (+d) or one step down (xe2x88x92d) with respect to the previous value. FIG. 1 shows a simple example of a conventional delta modulator/demodulator configuration 100. An analog signal is supplied to an input, sampled by a sample and hold circuit 110, and digitized by a digitizer 120. The digital samples are then supplied to a non-negating input of a subtractor 130. A negating input of the subtractor 130 receives a reconstructed signal (image). The subtractor 130 then determines the difference between the supplied digital sample and a sample from the reconstructed signal (image). This difference is supplied to a limiter 140. Only the sign of the difference is of interest. Consequently, the output of the limiter 140 supplies bits 0/1 where, for example, a 0 means that a negative difference was detected and 1 means that a positive difference was detected. The output of the limiter 140 is the output of the delta modulator 180, and is therefore transferred to a delta demodulator 190. Within the delta modulator 180, the output of the limiter 140 is also used to control a feedback circuit that includes an accumulator 150. The output of the limiter 140 indicates whether a step xcex4 is to be added (bit=1) or subtracted (bit=0) from the value stored in the accumulator 150. The output of the accumulator 150 is the reconstructed signal (image) that is supplied to the negating input of the subtractor 130.
The delta demodulator 190 simply contains an accumulator 160 that stores a value to which either a step xcex4 is added (if the received input bit=1) or subtracted (if the received input bit=0). Finally, the digitized output of the accumulator 160 is filtered in a low-pass filter 170. The output of the low-pass filter 170 is an analog signal that should substantially resemble the one initially supplied to the sample and hold circuit 110. The modulation and demodulation processes may further contain upsampling and downsampling, but these functions are not shown in order to simplify the explanation of the pertinent details.
The simple delta modulation technique described above does not give acceptable performance when a voice signal is considered. The dynamics in the voice signal are large and it is difficult to find a suitable step size in the delta modulator that is both small enough to hide quantization noise, and large enough to be able to follow large escapes in the voice signal. If the step size is chosen small enough to reduce noise, a phenomenon called xe2x80x9cslope overloadxe2x80x9d typically results, in which the signal reconstructed from the delta values is unable to accurately reproduce the original signal. An example of slope overload is illustrated in the graph of FIG. 2. An original analog signal 201 is shown. The step-wise signal 203 is generated at the outputs of the accumulators 150 and 160. The derivative of the original signal 201 is much larger than the step size in the delta modulator. Consequently, a long sequence of positive or negative delta values is generated, such as the sequence of negative values 205. However, the relatively small step size in the modulator prevents the reconstructed step-wise signal 203 from following the original signal 201.
To avoid slope overload problems, a modification in the delta modulator has been developed in which the step size dynamically changes: If the signal involves large variations, the step size is increased; and if the signal is rather stable, the step size is decreased. In this way, the instantaneous signal-to-quantization noise ratio is kept fairly constant whereas large changes in the signal can be followed. Such a system is referred to as a Continuous Variable Slope Delta (CVSD) modulator, since the step size varies depending on the slopes in the input signal.
A CVSD modulator/demodulator configuration is shown in FIG. 3. An analog signal is supplied to an input, sampled by a sample and hold circuit 110, and digitized by a digitizer 120. The digital samples are then supplied to a CVSD encoder 301. Within the CVSD encoder 301, the digital samples are supplied to a non-negating input of a subtractor 330. A negating input of the subtractor 330 receives a reconstructed signal (image). The subtractor 330 then determines the difference between the supplied digital sample and a sample from the reconstructed signal (image). This difference is supplied to a limiter 340. Only the sign of the difference is of interest. Consequently, the output of the limiter 340 supplies bits 0/1 where, for example, a 0 means that a negative difference was detected and 1 means that a positive difference was detected. The output of the limiter 340 is the output of the CVSD encoder 301, and is therefore transferred to a CVSD decoder 303.
Within the CVSD encoder 301, the output of the limiter 340 is also used to control a feedback circuit that includes an accumulator 350. The output of the limiter 340 is supplied to the accumulator, and controls whether a step xcex4 is to be added (bit=1) or subtracted (bit=0) from the value stored in the accumulator 350. The output of the accumulator 350 is the reconstructed signal (image) that is supplied to the negating input of the subtractor 330.
The CVSD encoder 301 differs from the delta modulator 180 in that it further includes a step size generator 310, which generates a step size based on the signal supplied at the output of the limiter 340. The output of the step size generator 310 is supplied to the accumulator 350, and represents the step xcex4 that should alternatively be added to, or subtracted from, the existing contents of the accumulator 350, as determined by the value supplied by the limiter 340. Thus, instead of a fixed step size xcex4, as is used in the configuration of FIG. 1, the step size 6 in the configuration of FIG. 2 is varied and depends on the number of 1s or 0s produced in the sequence generated by the limiter 340.
The CVSD decoder 303 is similarly arranged to utilize variable-sized steps. In the exemplary arrangement, the CVSD decoder 303 contains an accumulator 60 that stores a value to which either a step xcex4 is added (if the received input bit=1) or subtracted (if the received input bit=0). The size of the step 6 that is added or subtracted is generated by a step size generator 370, and depends on the sequence of 1s or 0s produced in the sequence generated by the CVSD encoder 301. Finally, the digitized output of the accumulator 360 is filtered in a low-pass filter 170. The output of the low-pass filter 170 is an analog signal that should substantially resemble the one initially supplied to the sample and hold circuit 110. The modulation and demodulation processes may further contain upsampling and downsampling, but these functions are not shown in order to simplify the explanation of the pertinent details.
The use of CVSD technology reduces slope-overload deficiencies described above. This improvement is illustrated in the graph of FIG. 4, which shows the same original analog signal 201 as in FIG. 2, and the improved tracking of the reconstructed step-wise signal 401 generated by the accumulators 350 and 360. The CVSD technique is well-known. For example, a description can be found in xe2x80x9cDigital Coding of Waveforms,xe2x80x9d by N. S. Jayant and P. Noll (Prentice-Hall, Inc. New Jersey, 1984).
The process of varying the step size is also referred to as syllabic companding. The use of syllabic companding improves the voice quality because it more accurately follows the voice signal while not compromising on the Signal-to-Noise Ratio (SNR). But this only holds true for an error-free environment. In an error-prone environment, such as is often encountered in a radio communications environment, the use of syllabic companding makes the signal less robust. This is because errors in the bits to be decoded will not only affect the step sign, but also the step size d. In particular, burst errors (i.e., errors that affect an entire group of bits that are transmitted in sequence) may cause the recipient to erroneously determine the existence of a large slope in the signal, which in turn will cause the step size to be erroneously increased. This, in turn, results in a reconstructed signal having an increased signal level which may be noticeable as clicks and cracks to the listener.
There is, therefore, a need for methods and apparatuses that provide robustness in CVSD demodulators disturbed by bursty interference.
It should be emphasized that the terms xe2x80x9ccomprisesxe2x80x9d and xe2x80x9ccomprisingxe2x80x9d, when used in this specification, are taken to specify the presence of stated features, integers, steps or components; but the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.
In accordance with one aspect of the invention, the foregoing and other objects are achieved in methods and apparatuses that generate a step size for use in a continuous variable slope delta demodulator. This is accomplished by determining a likelihood that a group of one or more coded bits includes an erroneous bit, and then generating the step size as a function of the likelihood that the group of one or more coded bits includes an erroneous bit.
For example, the step size may be increased by a greater amount if the likelihood that the group of one or more coded bits includes an erroneous bit is not greater than a threshold value, whereas the step size may be increased by a lesser amount (or not at all) if the likelihood of an error is greater than the threshold value.
Alternatively, the step size may be increased at a slower rate when errors are likely than is used when errors are not likely.
Combinations of these approaches may also be performed.
In another alternative, a next step size, xcex4NEXT may be set in accordance with the following:
xcex4NEXT=xcex4PREVIOUS+xcex4ERROR
if J of the most recently received K bits are equal to one another, otherwise,
xcex4NEXT=xcex2xc2x7xcex4PREVIOUS
wherein:
xcex4PREVIOUS is a previous value of the step size;
xcex2 is a constant in the range between zero and one;
K is a number greater than one;
J is a number in the range from one to K; and
xcex4ERROR has a value that is inversely proportional to an error rate associated with the group of one or more coded bits.
In yet another alternative, a next step size, xcex4NEXT, may be set in accordance with the following:
xcex4NEXT=xcex4PREVIOUS+xcex4ERROR
if J of the most recently received K bits are equal to one another, otherwise,
xcex4NEXT=xcex2xc2x7xcex4PREVIOUS
wherein:
xcex4PREVIOUS is a previous value of the step size;
xcex2 is a constant in the range between zero and one;
xcex4ERROR is a number greater than zero;
K is a number greater than one;
J is a number in the range from one to K; and
values for K and J are selected as a function of an error rate associated with the group of one or more coded bits. In some embodiments, selecting values for K and J is performed in such a way that a rate at which xcex4NEXT increases is inversely proportional to the error rate associated with the group of one or more coded bits. Embodiments utilizing this approach may optionally also give xcex4ERROR a value that is inversely proportional to an error rate associated with the group of one or more coded bits.